PLLs are commonly used in radio systems to stabilize the output phase of a voltage controlled oscillator (VCO). PLLs generally comprise a VCO enveloped by a control loop comprising; a frequency divider for dividing the frequency of the VCO by a divisor; a phase detector and stable frequency reference for generating a voltage or current analogue of the phase difference between the divided VCO signal and the stable reference; and a loop filter for producing a VCO control voltage from the phase detector output. A direct digital modulating PLL induces a modulation of the VCO output phase by varying the divisor of the frequency divider.
In the Global System for Mobile communication (GSM) standard, the transmit VCO must be able to lock a 100 MHz step to better than 90 Hz accuracy in under 200 microseconds. This is due to the need to minimize current drain by turning the transmit subsystem OFF when not in use and restart quickly upon turn ON. It is furthermore important that this specification be met over a significant range of temperature and part variations.
Direct digital modulation is highly desirable, but very difficult to accommodate, in such an environment. Avoiding distortion of the modulation is perhaps the most difficult challenge. In GSM systems, the measure of modulation distortion is the global phase error standard, which imposes a modulation phase distortion limit of 5 degrees rms.
To achieve low distortion of the modulation phase, the PLL loop filter must be carefully designed for phase linearity as well as for the usual design criteria of stability, lock time and PLL bandwidth.
Modulated signals have a spectrum characterized by a modulation bandwidth. The modulation bandwidth is the frequency range, offset from the channel center, in which the spectral power of the modulation resides. In GSM systems the modulation bandwidth is approximately 100 KHz. Direct digital modulation requires a PLL band width to be greater than the modulation bandwidth in order to avoid attenuation of the modulation content at the higher offset frequencies.
Further challenging the successful completion of a direct digital modulating PLL is the need to suppress unwanted spurious emissions. In GSM systems, the output radio frequency (RF) spectrum due to the modulator must be suppressed by 30 dBC at 200 KHz offset from the carrier, and by 60 dBC at 400 KHz offset from the carrier. The GSM specification further requires that spurious emissions at a frequency offset greater than 1.8 MHz from the channel center have a power level below 30 dBm. These restrictions on spurious emissions impose upper limits on the PLL bandwidth.
When a phase-locked loop (PLL) must tune rapidly over a wide frequency range, produce low modulation distortion that dictates wide PLL bandwidth, and produce low spurious emissions that dictate high selectivity, conventional loop filter configurations can be inadequate. A conventional type II PLL can provide rapid tuning over a wide range, but good selectivity generally leads to a compromise in modulation fidelity.
It is therefor desirable to provide an improved PLL.